Each generation of dynamic random access memory (DRAM) typically doubles the amount of data that is pre-fetched during a memory access. For example, double data rate (DDR) 2 pre-fetches twice as much data as DDR1. Similarly, DDR3 pre-fetches twice as much data as DDR2. The width of the internal DRAM bus increases with the amount of data that is pre-fetched. As the width of the internal DRAM bus increases, the die size of the DRAM also increases.
DRAM is available in different device widths such as x4, x8, x16, and the like. The term “device width” refers to the width of the external DRAM bus with which a DRAM is designed to interoperate. Currently x4 and x8 wide DRAM devices have a page size of 1K Bytes and x16 wide DRAM devices have a page size of 2K Bytes. A “page” refers to the number of bits that are activated by a row address strobe (RAS) command.